At present, reduction of power consumption is required of portable apparatuses, such as portable telephones, notebook computer type apparatuses, and palmtop computer type apparatuses.
FIG. 1 shows an example how a portable apparatus according to conventional technology is configured. The portable apparatus shown therein includes a memory 10 consisting of DRAMs, a DRAM controller 20, an image-processing unit (IP: image processor) 30, a central processing unit (CPU) 40, an interface 50, and a system power circuit 60. The IP 30 and the CPU 40 can simultaneously access the memory 10 through the DRAM controller 20. That is, the IP 30 and the CPU 40 share a data bus and a command bus (data/command bus) 70. The IP 30 and the CPU 40 transmit and receive data to and from an external apparatus, which is not illustrated, through the interface 50 that is connected to an external I/O terminal.
The CPU 40 controls the system power circuit 60 by a power control signal A. The system power circuit 60 supplies power to the internal circuit of the portable apparatus. In FIG. 1, a power supply path to a peripheral circuit 11b of a memory core 11d of the memory 10 is illustrated, for example. When, for example, the portable apparatus is put to a resume mode (stand-by mode, idle status), the CPU 40 outputs the power control signal A to the system power circuit 60 such that the internal circuit including the memory 10 is put to a low-power mode. The memory 10 that is put to the low-power mode is supplied with necessary minimum power required in order that the peripheral circuit 11b keeps operating, and power consumption is reduced.
As mentioned above, the IP 30 and the CPU 40 can simultaneously access the memory 10. Accordingly, in order to share the memory 10, the access rate should be twice as high as the case wherein the IP 30 and the CPU 40 independently access the memory 10. For example, when the independent access rate of each the IP 30 and the CPU 40 is 50 MHz, in order to share the memory 10, an access rate of 100 MHz is required.
While simultaneous access is possible, the IP 30 and the CPU 40 do not necessarily operate (access the memory 10) simultaneously in fact, and often, only the CPU 40 accesses the memory 10. In other words, the operating time of the CPU 40 is greater than the operating time of the IP 30. If there are no data that should be processed, the IP 30 does not perform image processing, but is in an idle status.
Even if the IP 30 is in the idle status, the access rate is not changed. In the above-mentioned example, the access rate remains at 100 MHz. In order for only the CPU 40 to access the memory 10, the access rate can be lowered to 50 MHz. That is, when the IP 30 is in the idle status, power is consumed uselessly. Generally, portable apparatuses operate on rechargeable batteries and dry cells. Therefore, if the IP 30 is in the idle status, built-in battery energy is uselessly consumed, and the operating time of the portable apparatus becomes short.
The problem is similarly applicable to systems that share a memory between two or more units and circuits.